Low Power FinFET Based Full Adder Design

Abstract: The great challenge in the nanometer regime is due to Short Channel Effects that cause an exponential increase in the leakage current. With the advancement in technology, Conventional CMOS has Short Channel Effects. In order to reduce the Short Channel Effects, FinFET is used. FinFETs are the new emerging transistors that can work in the nanometer range to overcome these Short Channel Effects. The Low Power FinFET based Full Adder is implemented by using CADENCE VIRTUOSO tools in 45nm technology with the supply voltage of 1V in CMOS and 15nm technology with the supply voltage of 0.7V in FinFET. The Simulation is done to compare power, delay and power- delay product. The result shows that the PDP of GDI FinFET Full Adder is reduced to 67% compared to FinFET Full Adder.

Keywords: Low Power; Full Adder; CMOS; FinFET; GDI.