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Low Power Full Adder Circuit Implementation using Transmission Gate
Akansha Maheshwari, Surbhit Luthra
DOI: 10.17148/IJARCCE.2015.4741
Abstract: In this paper, the power consumption of a conventional full adder circuit is reduced by using transmission gate at the place of pass transistor logic (NMOS or PMOS). This circuit is designed using 100nm technology parameters.
Keywords: power; full adder circuit; transmission gate; pass transistor; NMOS; PMOS.
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This work is licensed under a Creative Commons Attribution 4.0 International License.How to Cite:
[1] Akansha Maheshwari, Surbhit Luthra, “Low Power Full Adder Circuit Implementation using Transmission Gate,” International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE), DOI: 10.17148/IJARCCE.2015.4741