📞 +91-7667918914 | ✉️ ijarcce@gmail.com
IJARCCE Logo
International Journal of Advanced Research in Computer and Communication Engineering A monthly Peer-reviewed & Refereed journal
ISSN Online 2278-1021ISSN Print 2319-5940Since 2012
IJARCCE adheres to the suggestive parameters outlined by the University Grants Commission (UGC) for peer-reviewed journals, upholding high standards of research quality, ethical publishing, and academic excellence.
← Back to VOLUME 4, ISSUE 3, MARCH 2015

Performance Based Comparative Analysis of MOS Structures at 32nm and 20nm Node

Pallavi Choudhary,Tarun Kapoor

DOI: 10.17148/IJARCCE.2015.4334

Abstract: MOSFETs have always been the workhorse of semiconductor industry, with passing decades the sizes of MOSFETs have been continuously decreasing. This is guided by decrease in the gate length or channel length. However decrease in channel length of planar MOSFETs has reached its saturation level due to short channel effects and DIBL. In this paper we have tried to present an electrical comparison between 32nm node technology and 20nm node technology of planar MOS structures. The structures have been fabricated using SILVACO TCAD software and study of threshold voltages and corresponding oxide thickness has been made.

 



Keywords: 35 nmPMOS, 20 nm PMOS, Threshold Voltage, Oxide Thickness, SILVACO TCAD, Athena.

How to Cite:

[1] Pallavi Choudhary,Tarun Kapoor, “Performance Based Comparative Analysis of MOS Structures at 32nm and 20nm Node,” International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE), DOI: 10.17148/IJARCCE.2015.4334