Performance Enhancement in Combinational Circuit using Gate Diffusion Technique

Abstract: Low power circuit design has been an important issue in VLSI design areas. Full adders are important components in application such as digital signal processors (DSP) and microprocessors. The full adder design can be designed by using conventional CMOS and positive feedback adiabatic logic (PFAL). The more number of transistors and more power can be needed. Gate diffusion technique (GDI) can be used to implement the full adder design. This technique allows the low power consumption and area of digital circuits while maintaining low complexity of logic design. In this work, the number of transistor and power of the conventional CMOS, positive feedback adiabatic logic (PFAL) and gate diffusion technique (GDI) are compared. Tanner EDA tool can be used for simulation.

Keywords: Full adder, multiplexer, conventional CMOS, Positive feedback adiabatic logic (PFAL), Gate diffusion input (GDI) technique.