Performance Evaluation of 6 Transistor D-Flip Flop based Shift Registers using GDI Technique

[1] M.ARUNLAKSHMAN, T.DINESHKUMAR, N.MATHAN M.Tech VLSI, Sathyabama University, Chennai, India M.Tech VLSI, Sathyabama University, Chennai, India Assistant Professor ECE, Sathyabama University, Chennai, India, “Performance Evaluation of 6 Transistor D-Flip Flop based Shift Registers using GDI Technique,” International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE)