Performance Evaluation of 6 Transistor D-Flip Flop based Shift Registers using GDI Technique

Abstract: Power dissipation is an important parameter in the design of VLSI circuits, and the clock network is responsible for a substantial part of it (up to 50%). Low Power digital CMOS becomes more and more interesting, due to the general advances in process technology and due to new low power applications. As technology advances push for smaller devices and faster operations, power consumption and become severe problems when designing high-speed ICs. These challenging concerns are mainly due to the excessive switching activity in the chip that keeps increasing proportionally to the frequency augment and the number of transistors. In this paper a new 6 transistor D-Flip-Flop based on GDI technique is designed and Shift Registers including Serial in Serial out (SISO), Serial in Parallel out (SIPO), Parallel in Serial Out (PISO), Parallel in Parallel Out (PIPO) are designed based on this newly designed D-Flip-Flop and layouts are also designed using Microwind.

Keywords: Flip-Flop, Shift Registers, GDI technique, Power, Layout.