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Performance Evaluation of 6 Transistor D-Flip Flop based Shift Registers using GDI Technique
M.ARUNLAKSHMAN, T.DINESHKUMAR, N.MATHAN M.Tech VLSI, Sathyabama University, Chennai, India M.Tech VLSI, Sathyabama University, Chennai, India Assistant Professor ECE, Sathyabama University, Chennai, India
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This work is licensed under a Creative Commons Attribution 4.0 International License.How to Cite:
[1] M.ARUNLAKSHMAN, T.DINESHKUMAR, N.MATHAN M.Tech VLSI, Sathyabama University, Chennai, India M.Tech VLSI, Sathyabama University, Chennai, India Assistant Professor ECE, Sathyabama University, Chennai, India, βPerformance Evaluation of 6 Transistor D-Flip Flop based Shift Registers using GDI Technique,β International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE)