Recovery Boosting Technique for Improving NBTI Recovery in SRAM Arrays

Abstract: Negative bias temperature instability (NBTI) is an important Lifetime reliability problem in microprocessors. In order to overcome this problem many techniques has been initialized but all those results in Time delay and Instability that affects the performance of micro processors adversely, actually the Recovery boosting techniques and stress bias techniques are used for solving the performance problems. In this project a basic 6T SRAM is taken for the testing. SRAM is comprised of PMOS and NMOS, PMOS create the problem of NBTI as it is less stabilized in normal recovery boosting techniques an extra inverter is added and the output will be noted , by this process the NBTI reduced but that results in increased power and delay of the SRAM, this affects the performance of SRAM. In Fine Grained recovery boosting an extra PMOS inverter is added to this normal circuit while checking the circuit showed better power , delay and resistance to NBTI. After that 4T SRAM array is constructed. After that a memory system is designed.

Keywords: NBTI, PMOS, NMOS, SRAM, Fine Grained recovery boosting