Ultra Low Power VLSI Design used to Reduce Sub Threshold Leakage Power

Abstract: Leakage power plays a vital role in current CMOS technologies. As feature size shrinks leakage power also increasing. Power dissipation becomes as important consideration as performance and area for chip design in present days VLSI industry. International Technology Roadmap for Semiconductors (ITRS) forecasts that sub threshold leakage power dissipation may dominate the dynamic power dissipation. There are two types of power dissipations in CMOS technologies those are static power dissipation and Dynamic power Dissipation. This paper mainly concentrates on static power dissipation, in that mainly on leakage power. This paper reviews various low leakage power design techniques to achieve low power dissipation.

Keywords: Leakage power, power Dissipation, low power, CMOS technologies.