Optimization Of A Full adder Based On FinFET Technology

Abstract: In this paper, an adder circuit are designed in which full adder cmos is included, are designed using MOSFET in 32nm Technology length and in FinFET Technology with 28 transistors in MOSFET and FINFET. Then, they are simulated using HSPICE and the performance parameters of adder such as average power and delay are determined in both FinFET and MOSFET counterpart. It is observed that FAFINFET gives best results in the form of Average Power consumption and delay.

Keywords: Ripple Carry Adder, FinFET, 32nm