“OPTIMIZED VLSI DESIGN FOR REAL-TIME EDGE DETECTION"

Abstract: Edge detection is a foundational operation in computer vision and embedded image processing, enabling systems to identify structural boundaries and salient features within visual data. Real-time implementation of edge detection remains challenging in software platforms due to high computational load and latency. To address this limitation, a hardware-optimized VLSI architecture implementing the Sobel operator is proposed for real-time video edge extraction. The system acquires live frames through a VGA camera, performs grayscale conversion, calculates horizontal and vertical gradients using Sobel convolution masks, and computes edge magnitude before applying thresholding. Implemented on the Artix-7 FPGA using Verilog HDL, the design leverages parallelism, pipelining, on-chip memory optimization, and low-power computation. Experimental evaluation demonstrates significant improvements in throughput, latency, and resource efficiency over traditional software-based methods. The architecture is suitable for embedded vision applications such as surveillance, robotics, and smart IoT cameras. .

Keywords: Sobel, VLSI, FPGA, Edge Detection, Verilog, Real-Time Video Processing.