Power-Delay Behaviour of Digital Circuits Designed using MOSFET, CNTFET and FinFET, with the Scope of Miniaturization in these Transistors

Abstract: In current scenario, power–delay trade-off and downsizing in deep submicron transistors is major area of innovation. Double gated MOSFET (also called FinFET) and CNTFET are the apt substitutes to the MOSFET at the nanometer scale. MOSFET experiences sub threshold conduction at the nanometer scale, which hinders its performance. If conventional MOSFET is replaced by FinFET, a better control over its channel can be obtained which will avert sub threshold conduction in it. While replacing MOSFET with optimized CNTFET, the prevailing conduction mechanism of its charge carriers through its channel is totally replaced by novel ballast transport mechanism through the Carbon Nanotube (CNT). In this paper, power dissipation and delay in the digital applications based on above transistors are evaluated. Here Synopsis HSPICE tool is used for simulation.

Keywords: FinFET, Nanotubes, Carbon nanotube FET, Multipliers