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An Efficient Field Programmable Gate Array Implementation of Fully Pipelined Advanced Encryption Standard Algorithm using VHDL
PARAMVEER KAUR, PARMINDER SINGH JASSAL M.Tech, student, ECE, Yadvindra College of Engineering , Talwandi Sabo (Pb)-India Assistant Professor, ECE, Yadvindra College of Engineering, Talwandi Sabo (Pb)-India
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Abstract: The Advanced Encryption Standard (AES) was approved after a lengthy public review by the National Institute for Standards and Technology (NIST) as the encryption process to replace the Data Encryption Standard (DES) once it was broken. AES is now gaining fast acceptance around the world. This paper presents the hardware implementation of the AES encryption which proves to be more secure as its software counterpart.
Keywords: Advanced Encryption Standard, Data Encryption Standard, National Institute for Standards and Technology, Field Programmable Gate Array.
Keywords: Advanced Encryption Standard, Data Encryption Standard, National Institute for Standards and Technology, Field Programmable Gate Array.
How to Cite:
[1] PARAMVEER KAUR, PARMINDER SINGH JASSAL M.Tech, student, ECE, Yadvindra College of Engineering , Talwandi Sabo (Pb)-India Assistant Professor, ECE, Yadvindra College of Engineering, Talwandi Sabo (Pb)-India , βAn Efficient Field Programmable Gate Array Implementation of Fully Pipelined Advanced Encryption Standard Algorithm using VHDL,β International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE)
This work is licensed under a Creative Commons Attribution 4.0 International License.