An HVD Based Error Detection and Correction Code in HDLC Protocol Used for Communication

Abstract: With the increase of data transmission and hence sources of noise and interference, engineers have been struggling with the demand for more efficient and reliable techniques for detecting and correcting errors in received data. Although several techniques and approaches have been proposed and applied in the last decade, data reliability in transmission is still a problem. In this report propose a high efficient combined error detection and correction technique based on the horizontal-vertical diagonal (HVD) parity check in HDLC. This method has been experimentally implemented and simulated using Field Programmable Gate Array .Simulation results show that the proposed technique detects 99.99% of the errors and corrects as predicted up to three bits of errors in the received impaired n-bit code. An independent design platform is utilized for the simulation by Xilinx 8.1 using ModelSim SE-EE 5.4a coded in VHDL which shows a significant reduction in uncorrected errors during data transmission. The efficient performance of HVD makes it a more applicable coding technique for communication, data transmission, different protocols and other application.

Keywords: EDAC (Error Detection and Correction), FPGA (Field Programmable Gate Array), HDLC (High Data Control Protocol), HVD (Horizontal Vertical Diagonal), ModelSim, VHDL (VHSIC Hardware Descriptive Language), Xilinx.