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Effective Implementation of SHA-1Algorithm using FPGA
SUNIL KUMAR TUDUMU, SYAMALA.K Student (M.Tech, VLSI-SD), Dept., of ECE, Avanthi Institute Of Engineering And Technology, Visakhapatnam, India Assistant Professor, Department of ECE, Avanthi Institute Of Engineering And Technology, Visakhapatnam, India
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Abstract: In this report Secure Hash Algorithm (SHA-1) is proposed and it is implemented to produce a single output 160- bit message digest (the output hash value) from an input message suing FPGA. The input message is composed of multiple blocks. For providing this output it uses many arithmetic and logical operations. The Secure Hashing Algorithm is issued by Federal Information Processing Standards Publications (FIPS PUBS) and National Institute of Standards and Technology (NIST) after approval by the Secretary of Commerce pursuant to Section 5131 of the Information Technology. βcryptographyβ by Information Security. The Modelsim.se.v6.2c is used for functional simulation of the SHA-1.
Keywords: SHA-1,algorithm, FPGA, modelSim
Keywords: SHA-1,algorithm, FPGA, modelSim
How to Cite:
[1] SUNIL KUMAR TUDUMU, SYAMALA.K Student (M.Tech, VLSI-SD), Dept., of ECE, Avanthi Institute Of Engineering And Technology, Visakhapatnam, India Assistant Professor, Department of ECE, Avanthi Institute Of Engineering And Technology, Visakhapatnam, India, βEffective Implementation of SHA-1Algorithm using FPGA,β International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE)
This work is licensed under a Creative Commons Attribution 4.0 International License.