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Optimization of Low Power CMOS based Voltage Reference Generator in 32nm
Sneha Meshram, Uday Panwar
DOI: 10.17148/IJARCCE.2018.7810
Abstract:
In this paper, a CMOS based low power voltage reference generator is optimized in 32nm technology. Circuit’s temperature dependencies and threshold voltage dependencies is studied and improved to give higher reference voltage generated in low power applications. The simulation are performed on Synopsys HSPICE software. Simulation results shows higher reference voltage is obtained with low power consideration and under different temperatures giving minimal variations over temperatures in the voltage reference output.
Keywords:
Voltage Reference, 32nm MOSFET, Analog Circuit, 32nm FinFET
[1] Sneha Meshram, Uday Panwar, “Optimization of Low Power CMOS based Voltage Reference Generator in 32nm,” International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE), DOI: 10.17148/IJARCCE.2018.7810
