Power Optimization in Multiplier using VHDL

Abstract- In the recent year growth of the portable electronics is forcing the designers to optimize the existing design for better performance. Multiplication is the most commonly used arithmetic operation in various applications like, DSP processor, math processor and in various scientific applications. Overall performance of these devices is strongly depends on the arithmetic circuits like multiplier. This paper presented detailed analysis of low power CMOS multiplier which is very important for today’s scientific application. Experimental results show that it saves 10% of power for random input. Higher power reduction can be achieved if the operands contain more 0’s than 1’s.